This webinar discusses emerging hardware/software stacks for next‑generation AI workloads across data centers, edge platforms, and embedded devices—where latency, energy, reliability, and data locality are first‑class constraints. How do key platform layers fit together, from compilers and runtimes to systems software and orchestration for heterogeneous compute. It will cover the scope of the architectural shifts needed as bottlenecks to move from compute to memory and communication—including memory‑centric approaches, modern interconnects, and acceleration paths that may move beyond classic von Neumann assumptions to improve efficiency, portability, and responsiveness. The discussion will be led by Björn Forsberg from Research Institute of Sweden (RISE) and joined by Philippe Bonnet (University of Copenhagen).
